"The Art of Verification with SystemVerilog Assertions should be required reading for verification professionals. It is a great reference for SystemVerilog Assertions and an excellent companion to the VMM for SystemVerilog."
Ed Cerny (former Co-chair) SystemVerilog Assertion Committee, Synopsys
Co-author VMM  for SystemVerilog
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The Art of Verification with SystemVerilog Assertions
  • Detailed explanations of sequences, properties, and assertion directives
  • Assertions for common problems
  • Identifying assertions for your design
  • Assertion methodology
  • Basics of model checking (formal verification)
  • Teaches SVA by example
  • Written in simple, easy to understand language

Price: $99.95
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The Art of Verification with VERA

Learn the basics of verification
  • Basics of verification methodology
  • Structured test planning
  • Basics of object oriented programming
  • Basics of constrained random
  • Basics of VERA language
  • Building testbenches with VERA
  • A complete testbench and testplan for an Ethernet MAC
Price: $99.95

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 Set of VERA and SVA Books
Includes:
  • One copy of  "The Art of Verification with SystemVerilog Assertions" 
  • One copy of "The Art of Verification with VERA"

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Price: $169.95